DDR3 is the third generation of Double Data Rate (DDR) SDRAM memory. Similar to DDR2, it is a continuing evolution of DDR memory technology that delivers higher speeds (up to 1600 MHz), lower power consumption and heat dissipation. It is an ideal memory solution for bandwidth hungry systems equipped with dual and quad core processors and the lower power consumption is a perfect match for both server and mobile platforms. Dual In-line Memory Modules, or DIMMs, closely resemble SIMMs. Like SIMMs, most DIMMs install vertically into expansion sockets. The principal difference between the two is that on a SIMM, pins on opposite sides of the board are tied together to form one electrical contact; on a DIMM, opposing pins remain electrically isolated to form two separate contacts.

JEDEC standard 1.5V ± 0.075V Power Supply

VDDQ = 1.5V ± 0.075V

533MHz fCK for 1066Mb/sec/pin

8 independent internal bank

Programmable CAS Latency: 6,7,8,9,10

Posted CAS

Programmable Additive Latency: 0, CL - 2, or CL - 1 clock

Programmable CAS Write Latency(CWL) = 7(DDR3-1066)

8-bit pre-fetch

Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS]

Bi-directional Differential Data Strobe

Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C

Asynchronous Reset

1066Mbps CL7 doesn’t have backward compatibility with 800Mbps CL5

PCB Height: 1.180 inch (30.00mm), double sided component